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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash
Rev. 02 -- 27 April 2010 Product data sheet
1. General description
The P89LPC970/971/972 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC970/971/972 in order to reduce component count, board space, and system cost.
2. Features and benefits
2.1 Principal features
2 kB/4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. 256-byte RAM data memory. Two analog comparators with selectable inputs and reference source. Five 16-bit counter/timers (each may be configured to toggle a port output upon timer overflow or to become a PWM output). A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit prescaler and a programmable and readable 16-bit timer. Enhanced UART with a fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 kHz byte-wide I2C-bus communication port. SPI communication port (pin remap). High-accuracy internal RC oscillator option 7.373 MHz calibrated to 1 %, with clock doubler option, allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. Watchdog timer with separate on-chip oscillator, nominal 400 kHz/25 kHz, calibrated to 10 % at 400 kHz, requiring no external components. The watchdog prescaler is selectable from eight values. Pin remap for UART, I2C-bus and SPI. 2.4 V to 5.5 V VDD operating range. Enhanced low voltage (brownout) detect allows a graceful system shutdown when power fails. 20-pin TSSOP and DIP packages with 15 I/O pins minimum and up to 18 I/O pins while using on-chip oscillator and reset options.
NXP Semiconductors
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
2.2 Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application. Clock switching on the fly among internal RC oscillator, watchdog oscillator, external clock source provides optimal support of minimal power active mode with fast switching to maximum performance. Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 A (total power-down with voltage comparators disabled). Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Idle mode, Power-down mode and total Power-down mode. In addition, the power consumption can be further reduced in Normal or Idle mode through configuring regulators modes according to the applications. Active-LOW reset. On-chip power-on reset allows operation without external reset components. A software reset function is also available. Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6, P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. Only power and ground connections are required to operate the P89LPC970/971/972 when internal reset option is selected. Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Emulation support.
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Product data sheet
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NXP Semiconductors
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
3. Ordering information
Table 1. Ordering information Package Name P89LPC970FDH P89LPC971FDH P89LPC972FDH P89LPC972FN TSSOP20 TSSOP20 TSSOP20 DIP20 Description plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic dual in-line package; 20 leads (300 mil) Version SOT360-1 SOT360-1 SOT360-1 SOT146-1 Type number
3.1 Ordering options
Table 2. Ordering options Flash memory 2 kB 4 kB 8 kB 8 kB Temperature range -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Frequency 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz Type number P89LPC970FDH P89LPC971FDH P89LPC972FDH P89LPC972FN
P89LPC97X_2
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NXP Semiconductors
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
4. Block diagram
P89LPC970/971/972
ACCELERATED 2-CLOCK 80C51 CPU
2 kB/4 kB/8 kB CODE FLASH 256-BYTE DATA RAM P3[1:0] PORT 3 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os
UART internal bus I2C-BUS
TXD RXD SCL SDA SPICLK(1) MOSI(1) MISO(1) SS(1)
SPI
P1[7:0]
REAL-TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 T0 T1 T2 T2EX T3 T3EX T4 T4EX CMP2 CIN2B CIN2A CMP1 CIN1A CIN1B
P0[7:0]
KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR
TIMER 2 TIMER 3 TIMER 4
PROGRAMMABLE OSCILLATOR DIVIDER
CPU clock
ANALOG COMPARATORS
XTAL1 CRYSTAL OR RESONATOR XTAL2
CONFIGURABLE OSCILLATOR
ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER
POWER MANAGEMENT (POWER-ON RESET, BROWNOUT RESET, REGULATORS)
002aae550
(1) For pin remap
Fig 1.
Block diagram
P89LPC97X_2
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Product data sheet
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
5. Functional diagram
VDD VSS
SPICLK(1)
T2 T3
KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7 CLKOUT
CMP2 CIN2B CIN2A CIN1B CIN1A CMPREF CMP1 T1 XTAL2
PORT 0
PORT 1
P89LPC970/ 971/972
TXD RXD T0 INT0 INT1 RST MISO(1) T3EX
T2EX SCL SDA T4EX MOSI(1)
T4 SS(1)
PORT 3 XTAL1
002aae551
(1) For pin remap
Fig 2.
Functional diagram
P89LPC97X_2
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Product data sheet
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
6. Pinning information
6.1 Pinning
P0.0/CMP2/KBI0/SPICLK P1.7/T3EX/MOSI P1.6/MISO P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1/T4EX/SS P1.3/INT0/SDA/T4
1 2 3 4 5 6 7 8 9
20 P0.1/CIN2B/KBI1 19 P0.2/CIN2A/KBI2 18 P0.3/CIN1B/KBI3/T2 17 P0.4/CIN1A/KBI4 16 P0.5/CMPREF/KBI5/T3 15 VDD 14 P0.6/CMP1/KBI6 13 P0.7/KBI7/T1 12 P1.0/TXD 11 P1.1/RXD/T2EX
002aae552
P89LPC970/971/972
P1.2/SCL/T0 10
Fig 3.
TSSOP20 pin configuration
P89LPC970/971/972
P0.0/CMP2/KBI0/SPICLK P1.7/T3EX/MOSI P1.6/MISO P1.5/RST VSS P3.1/XTAL1 P3.0/XTAL2/CLKOUT P1.4/INT1/T4EX/SS P1.3/INT0/SDA/T4 1 2 3 4 5 6 7 8 9 20 P0.1/CIN2B/KBI1 19 P0.2/CIN2A/KBI2 18 P0.3/CIN1B/KBI3/T2 17 P0.4/CIN1A/KBI4 16 P0.5/CMPREF/KBI5/T3 15 VDD 14 P0.6/CMP1/KBI6 13 P0.7/KBI7/T1 12 P1.0/TXD 11 P1.1/RXD/T2EX
002aae553
P1.2/SCL/T0 10
Fig 4.
P89LPC972 DIP20 pin configuration
P89LPC97X_2
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Product data sheet
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
6.2 Pin description
Table 3. Symbol Pin description Pin DIP20, TSSOP20 P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.16.1 "Port configurations" and Table 11 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt trigger inputs. Port 0 also provides various special functions as described below: P0.0/CMP2/KBI0/ SPICLK 1 I/O O I I/O P0.1/CIN2B/ KBI1 20 I/O I I P0.2/CIN2A/ KBI2 19 I/O I I P0.3/CIN1B/ KBI3/T2 18 I/O I I I/O P0.4/CIN1A/ KBI4 17 I/O I I P0.5/CMPREF/ KBI5/T3 16 I/O I I I/O P0.0 -- Port 0 bit 0. CMP2 -- Comparator 2 output KBI0 -- Keyboard input 0. SPICLK -- SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input (pin remap). P0.1 -- Port 0 bit 1. CIN2B -- Comparator 2 positive input B. KBI1 -- Keyboard input 1. P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. P0.3 -- Port 0 bit 3. High current source. CIN1B -- Comparator 1 positive input B. KBI3 -- Keyboard input 3. T2 -- Timer/counter 2 external count input or overflow output. P0.4 -- Port 0 bit 4. High current source. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. High current source. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. T3 -- Timer/counter 3 external count input or overflow output. Type Description
P89LPC97X_2
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
Table 3. Symbol
Pin description ...continued Pin DIP20, TSSOP20 Type Description
P0.6/CMP1/KBI6
14
I/O O I
P0.6 -- Port 0 bit 6. High current source. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. P0.7 -- Port 0 bit 7. High current source. KBI7 -- Keyboard input 7. T1 -- Timer/counter 1 external count input or overflow output. Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input-only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 7.16.1 "Port configurations" and Table 11 "Static characteristics" for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only. All pins have Schmitt trigger inputs. Port 1 also provides various special functions as described below:
P0.7/KBI7/T1
13
I/O I I/O
P1.0 to P1.7
I/O, I
[1]
P1.0/TXD P1.1/RXD/T2EX
12 11
I/O O I/O I I
P1.0 -- Port 1 bit 0. TXD -- Transmitter output for serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for serial port. T2EX -- Timer/counter 2 external capture input. P1.2 -- Port 1 bit 2 (open-drain when used as output). SCL -- I2C-bus serial clock input/output. T0 -- Timer/counter 0 external count input or overflow output. (open-drain when used as output.) P1.3 -- Port 1 bit 3 (open-drain when used as output). INT0 -- External interrupt 0 input. SDA -- I2C-bus serial data input/output. T4 -- Timer/counter 4 external count input or overflow output. P1.4 -- Port 1 bit 4. High current source. INT1 -- External interrupt 1 input. T4EX -- Timer/counter 4 external capture input. SS -- SPI Slave select input (pin remap). P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. P1.6 -- Port 1 bit 6. High current source. MISO -- SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output (pin remap).
P1.2/SCL/T0
10
I/O I/O I/O
P1.3/INT0/SDA/ T4
9
I/O I I/O I/O
P1.4/INT1/T4EX/ SS
8
I/O I I I
P1.5/RST
4
I I
P1.6/MISO
3
I/O I/O
P89LPC97X_2
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
Table 3. Symbol
Pin description ...continued Pin DIP20, TSSOP20 Type Description
P1.7/T3EX/MOSI
2
I/O I I/O
P1.7 -- Port 1 bit 7. High current source. T3EX -- Timer/counter 3 external capture input. MOSI -- SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input (pin remap). Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input-only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.16.1 "Port configurations" and Table 11 "Static characteristics" for details. All pins have Schmitt trigger inputs. Port 3 also provides various special functions as described below:
P3.0 to P3.1
I/O
P3.0/XTAL2/ CLKOUT
7
I/O O O
P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration. CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer. Ground: 0 V reference. Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P3.1/XTAL1
6
I/O I
VSS VDD
5 15
I I
[1]
Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P89LPC97X_2
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Product data sheet
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
7. Functional description
Remark: Please refer to the P89LPC970/971/972 User manual for a more detailed functional description.
7.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the SFRs. * SFR bits labeled `-', `0' or `1' can only be written and read as follows:
- `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
P89LPC97X_2
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Product data sheet
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* AUXR1 Accumulator Auxiliary function register B register E0H A2H Bit address B* F0H BEH CLKLP F7 EBRR F6 ENT1 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00 0000 000 0 0000 000 0 0000 000 0 xxxx xx00 Bit functions and addresses MSB E7 E6 E5 E4 E3 E2 E1 LSB E0 00 00 0000 000 0 0000 00x0 Reset value Hex Binary
Product data sheet Rev. 02 -- 27 April 2010 11 of 66
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BRGR0[1] Baud rate generator 0 rate low BRGR1[1] Baud rate generator 0 rate high BRGCO N CMP1 CMP2 DIVM Baud rate generator 0 control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low
BFH
00
8-bit microcontroller with accelerated two-clock 80C51 core
BDH
-
-
-
-
-
-
SBRGS
BRGEN
00[1]
ACH ADH 95H
-
-
CE1 CE2
CP1 CP2
CN1 CN2
OE1 OE2
CO1 CO2
CMF1 CMF2
00[2] 00[2] 00
xx00 0000 xx00 0000 0000 000 0
P89LPC970/971/972
DPTR DPH DPL
83H 82H E7H E6H
00 00 00 00
0000 000 0 0000 000 0 0000 000 0 0000 000 0
FMADRH Program flash address high FMADRL Program flash address low
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Table 4. Special function registers ...continued * indicates SFRs that are bit addressable. Name FMCON Description Program flash control (Read) Program flash control (Write) FMDATA I2ADR Program flash data I2C-bus slave address register I2C-bus control register I2C-bus data register Serial clock generator/SCL duty cycle register high Serial clock generator/SCL duty cycle register low I2C-bus status register Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high SFR addr. E4H E4H E5H DBH I2ADR.6 DF I2ADR.5 DE I2EN I2ADR.4 DD STA I2ADR.3 DC STO I2ADR.2 DB SI I2ADR.1 DA AA I2ADR.0 D9 GC D8 CRSEL 00 x000 00x0 Bit functions and addresses MSB BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1 LSB OI FMCMD. 0 00 00 0000 000 0 0000 000 0 Reset value Hex 70 Binary 0111 0000
Product data sheet Rev. 02 -- 27 April 2010 12 of 66
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Bit address I2CON* I2DAT I2SCLH D8H DAH
8-bit microcontroller with accelerated two-clock 80C51 core
DDH
00
0000 000 0
I2SCLL
DCH
00
0000 000 0
P89LPC970/971/972
I2STAT
D9H Bit address
STA.4 AF EA EF BF -
STA.3 AE EWDRT EE EST BE PWDRT PWDRTH
STA.2 AD EBO ED BD PBO PBOH
STA.1 AC ES/ESR EC EXTIM BC PS/PSR PSH/ PSRH
STA.0 AB ET1 EB ESPI BB PT1 PT1H
0 AA EX1 EA EC BA PX1 PX1H
0 A9 ET0 E9 EKBI B9 PT0 PT0H
0 A8 EX0 E8 EI2C B8 PX0 PX0H
F8
1111 1000
IEN0*
A8H Bit address
00
0000 000 0 00x0 0000
IEN1*
E8H Bit address
00[2]
IP0* IP0H
B8H B7H
00[2] 00[2]
x000 0000 x000 0000
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Table 4. Special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address IP1* IP1H KBCON Interrupt priority 1 Interrupt priority 1 high Keypad control register F8H F7H 94H 86H 93H Bit address P0* Port 0 80H 87 T1/KB7 86 CMP1/ KB6 96 B6 (P0M1.6) (P0M2.6) (P1M1.6) (P1M2.6) 85 CMPREF / KB5/T3 95 RST B5 (P0M1.5) (P0M2.5) 84 CIN1A/ KB4 94 INT1/ T4EX B4 (P0M1.4) (P0M2.4) (P1M1.4) (P1M2.4) 83 CIN1B/ KB3/T2 93 INT0/ SDA/T4 B3 (P0M1.3) (P0M2.3) (P1M1.3) (P1M2.3) 82 CIN2A/ KB2 92 T0/SCL B2 (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2) 81 CIN2B/ KB1 91 RXD/ T2EX B1 XTAL1 (P0M1.1) (P0M2.1) (P1M1.1) (P1M2.1) (P3M1.1) (P3M2.1) 80 Bit functions and addresses MSB FF FE PST PSTH FD FC PXTIM PXTIMH FB PSPI PSPIH FA PC PCH F9 PKBI PKBIH PATN _SEL LSB F8 PI2C PI2CH KBIF 00[2] 00[2] 00[2] 00 FF 00x0 0000 00x0 0000 xxxx xx00 0000 000 0 1111 1111 Reset value Hex Binary
Product data sheet Rev. 02 -- 27 April 2010 13 of 66
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NXP Semiconductors
KBMASK Keypad interrupt mask register KBPATN Keypad pattern register
8-bit microcontroller with accelerated two-clock 80C51 core
CMP2/ KB0 90 TXD B0 XTAL2
[2]
Bit address P1* Port 1 90H Bit address P3* P0M1 P0M2 P1M1 P1M2 P3M1 P3M2 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 3 output mode 1 Port 3 output mode 2 B0H 84H 85H 91H 92H B1H B2H
97 T3EX B7 (P0M1.7) (P0M2.7) (P1M1.7) (P1M2.7) -
[2]
[2]
P89LPC970/971/972
(P0M1.0) FF[2] (P0M2.0) 00[2] (P1M1.0) D3[2] (P1M2.0) 00[2] (P3M1.0) 03[2] (P3M2.0) 00[2]
1111 1111 0000 000 0 11x1 xx11 00x0 xx00 xxxx xx11 xxxx xx00
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 4. Special function registers ...continued * indicates SFRs that are bit addressable. Name PCON PCONA PINCON PMUCO N
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Product data sheet Rev. 02 -- 27 April 2010 14 of 66
P89LPC97X_2
NXP Semiconductors
Description Power control register Power control register A pin remap control register Power Management Unit control register Program status word Port 0 digital input disable PWM Free Cycle register 2 high byte
SFR addr. 87H B5H CFH FAH
Bit functions and addresses MSB SMOD1 RTCPD LPMOD SMOD0 VCPD BOI GF1 I2PD GF0 SPPD PMOD1 SPD SPI LSB PMOD0 HCOK
Reset value Hex 00 00[2] 00[2] Binary 0000 000 0 0000 000 0 0000 000 0 0xxx xxx1
Bit address PSW* PT0AD PWMD2 H D0H F6H AEH
D7 CY -
D6 AC -
D5 F0 PT0AD.5
D4 RS1 PT0AD.4
D3 RS0 PT0AD.3
D2 OV PT0AD.2
D1 F1 PT0AD.1
D0 P 00 00 00 0000 000 0 xx00 000x 0000 0000
8-bit microcontroller with accelerated two-clock 80C51 core
PWMD2L PWM Free Cycle register 2 low byte PWMD3 H PWM Free Cycle register 3 high byte
AFH
00
0000 0000
P89LPC970/971/972
E9H
00
0000 0000
PWMD3L PWM Free Cycle register 3 low byte PWMD4 H PWM Free Cycle register 4 high byte
EAH
00
0000 0000
AAH
00
0000 0000
PWMD4L PWM Free Cycle register 4 low byte RCAP2H Capture register 2 high byte
ABH
00
0000 0000
FCH
00
0000 0000
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Table 4. Special function registers ...continued * indicates SFRs that are bit addressable. Name RCAP2L Description Capture register 2 low byte SFR addr. FBH ECH EBH CAH C9H DFH D1H D2H D3H A9H B9H 99H Bit address SCON* SSTAT
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Bit functions and addresses MSB LSB
Reset value Hex 00 00 00 00 00 Binary 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
RCAP3H Capture register 3 high byte RCAP3L Capture register 3 low byte
RCAP4H Capture register 4 high byte RCAP4L Capture register 4 low byte
RSTSRC Reset source register RTCCON RTC control RTCH RTCL SADDR SADEN SBUF RTC register high RTC register low Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register
RTCF
BOIF RTCS1
BORF RTCS0
POF -
R_KB -
R_WD -
R_SF ERTC
R_EX RTCEN
[3]
60[2][4] 011x xx00 00[4] 00[4] 00 00 xx 0000 000 0 0000 000 0 0000 000 0 0000 000 0 xxxx xxxx
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC970/971/972
9F SM0/FE DBMOD
9E SM1 INTLO
9D SM2 CIDIS
9C REN DBISEL
9B TB8 FE
9A RB8 BR
99 TI OE
98 RI STINT 00 00 0000 000 0 0000 000 0 0000 0111 0000 010 0
98H BAH
SP SPCTL
81H E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0
07 04
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Table 4. Special function registers ...continued * indicates SFRs that are bit addressable. Name SPSTAT SPDAT TAMOD Description SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Timer/Counter 2 control Timer/Counter 2 high byte Timer/Counter 2 low byte Timer/Counter 3 control Timer/Counter 3 high byte Timer/Counter 3 low byte Timer/Counter 2 control SFR addr. E1H E3H 8FH Bit address TCON*
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Bit functions and addresses MSB SPIF WCOL LSB -
Reset value Hex 00 00 Binary 00xx xxxx 0000 000 0 xxx0 xxx0
8F TF1
8E TR1
8D TF0
T1M2 8C TR0
8B IE1
8A IT1
89 IE0
T0M2 88 IT0
00
88H 8CH 8DH 8AH 8BH 89H FFH FEH FDH EFH EEH EDH CDH
00 00 00 00 00
0000 000 0 0000 000 0 0000 000 0 0000 000 0 0000 000 0 0000 0000 0000 000 0 0000 000 0 0000 0000 0000 000 0 0000 000 0 0000 0000 0000 000 0
TH0 TH1 TL0 TL1 TMOD T2CON TH2 TL2 T3CON TH3 TL3 T4CON
8-bit microcontroller with accelerated two-clock 80C51 core
T1GATE PSEL2
T1C/T ENT2
T1M1 TIEN2
T1M0 PWM2
T0GATE EXEN2
T0C/T TR2
T0M1 C/NT2
T0M0
00
CP/NRL2 00 00 00
P89LPC970/971/972
PSEL3
ENT3
TIEN3
PWM3
EXEN3
TR3
C/NT3
CP/NRL3 00 00 00
PSEL4
ENT4
TIEN4
PWM4
EXEN4
TR4
C/NT4
CP/NRL4 00
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Table 4. Special function registers ...continued * indicates SFRs that are bit addressable. Name TH4 TL4 TINTF Description Timer/Counter 4 high byte Timer/Counter 4 low byte Timer/Counters 2/3/4 overflow and external flags Internal oscillator trim register Watchdog control register Watchdog load SFR addr. CCH CBH CEH TF4 EXF4 TF3 EXF3 TF2 EXF2 Bit functions and addresses MSB LSB Reset value Hex 00 00 00 Binary 0000 000 0 0000 0000 0000 000 0
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TRIM
96H
RCCLK
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0
[4][5]
WDCON WDL
A7H C1H C2H C3H
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
[4][6]
8-bit microcontroller with accelerated two-clock 80C51 core
FF
1111 1111
WFEED1 Watchdog feed 1 WFEED2 Watchdog feed 2
[1] [2] [3] [4] [5] [6]
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. All ports are in input only (high-impedance) state after power-up. The RSTSRC register reflects the cause of the P89LPC970/971/972 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. The only reset sources that affect these SFRs are power-on reset and watchdog reset. On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF.
P89LPC970/971/972
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Table 5. Name BODCFG Extended special function registers[1] Description BOD configuration register Clock control register Comparator reference register Real-time clock data register high SFR addr. Bit functions and addresses MSB FFC8H LSB BOICFG2 BOICFG1 BOICFG0 Reset value Hex
[2]
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Binary
CLKCON CMPREF
FFDEH FFCBH
CLKOK -
REFS5
WDMOD REFS4
XTALWD REFS3
CLKDBL -
FOSC2 REFS2
FOSC1 REFS1
FOSC0 REFS0
[3]
1000 xxxx 0000 0000 0000 0000 0000 0000
00
RTCDAT H
FFBFH
00
RTCDATL Real-time clock data register low
[1] [2] [3]
FFBEH
00
8-bit microcontroller with accelerated two-clock 80C51 core
Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs. The BOICFG2/1/0 will be copied from UCFG1.5 to UCFG1.3 when power-on reset. CLKCON register reset value comes from UCFG1. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG1.7.
P89LPC970/971/972
NXP Semiconductors
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
7.2 Enhanced CPU
The P89LPC970/971/972 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC970/971/972 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 5) and can also be optionally divided to a slower frequency (see Section 7.11 "CCLK modification: DIVM register"). Remark: fosc is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. The clock doubler option, when enabled, provides an output frequency of 14.746 MHz. PCLK -- Clock for the various peripheral devices and is CCLK2.
7.3.2 CPU clock (OSCCLK)
The P89LPC970/971/972 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.
7.4 Crystal oscillator option
The crystal oscillator option can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, RTC and WDT.
7.4.1 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.
7.4.2 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
7.4.3 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.
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7.5 Clock output
The P89LPC970/971/972 supports a user-selectable clock output function on the P3.0/XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC970/971/972. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
7.6 On-chip RC oscillator option
The P89LPC970/971/972 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. When clock doubler option is enabled, BOE0 to BOE2 bits (UCFG1[3:5]) are required to hold the device in reset at power-up until VDD has reached its specified level.
7.7 Watchdog oscillator option
The watchdog has a separate oscillator which provides two options: 400 kHz and 25 kHz. It is calibrated to 10 % at 400 kHz. The oscillator can be used to save power when a high clock frequency is not needed.
7.8 External clock input option
In this configuration, the processor clock is derived from an external source driving the P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2/CLKOUT pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, BOE0 to BOE2 bits (UCFG1[3:5]) are required to hold the device in reset at power-up until VDD has reached its specified level.
7.9 Clock source switching on the fly
P89LPC970/971/972 can implement clock switching on any sources of watchdog oscillator, 7 MHz/14 MHz internal RC oscillator, crystal oscillator and external clock input during code is running. CLKOK bit in CLKCON register is used to indicate the clock switch status. CLKOK is cleared when starting clock source switch and set when completed. Notice that when CLKOK is `0', writing to CLKCON register is not allowed.
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8-bit microcontroller with accelerated two-clock 80C51 core
XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY
RTC
OSCCLK RC OSCILLATOR WITH CLOCK DOUBLER RCCLK
DIVM
CCLK /2 PCLK
CPU
(7.3728 MHz/14.7456 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz/25 kHz 10 %) TIMER 0/ TIMER 1 PCLK
WDT
TIMER 2/ TIMER 3/ TIMER 4
SPI(1)
UART
I2C-BUS
002aae554
(1) 10 % at 400 kHz.
Fig 5.
Block diagram of oscillator control
7.10 CCLK wake-up delay
The P89LPC970/971/972 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 s to 100 s. If the clock source is the internal RC oscillator, the delay is 200 s to 300 s. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.
7.11 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
7.12 Low power select
The P89LPC970/971/972 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
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8-bit microcontroller with accelerated two-clock 80C51 core
7.13 Memory organization
The various P89LPC970/971/972 memory spaces are as follows:
* DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
* IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
* SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
* XDATA
`External' Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip.
* CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC970/971/972 has 4 kB/8 kB of on-chip Code memory.
7.14 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 6.
Table 6. Type DATA IDATA XDATA On-chip data memory usages Data RAM Memory that can be addressed directly and indirectly Memory that can be addressed indirectly Auxiliary (External Data) on-chip memory that is accessed using the MOVX instructions Size (bytes) 128 256 256
7.15 Interrupts
The P89LPC970/971/972 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC970/971/972 supports 15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, timer 2/3/4, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but
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not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
7.15.1 External interrupt inputs
The P89LPC970/971/972 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON. In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request. If an external interrupt is enabled when the P89LPC970/971/972 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.17.3 "Power reduction modes" for details.
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
IE0 EX0 IE1 EX1 BOIF EBO RTCF ERTC WDOVF KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI and RI/RI ES/ESR TI EST SI EI2C SPIF(1) ESPI(1) TF2 EXF2 TIEN2 TF3 EXF3 TIEN3 TF4 EXF4 TIEN4 EXTIM interrupt to CPU
wake-up (if in power-down)
002aae555
(1) For pin remap.
Fig 6.
Interrupt sources, interrupt enables, and power-down wake-up sources
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7.16 I/O ports
The P89LPC970/971/972 has four I/O ports: Port 0, Port 1 and Port 3. Ports 0, 1 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 7.
Table 7. Number of I/O pins available Reset option Number of I/O pins (20-pin package) 18 17 17 16 16 15
Clock source
On-chip oscillator or watchdog oscillator External clock input
no external reset (except during power-up) external RST pin supported no external reset (except during power-up) external RST pin supported no external reset (except during power-up) external RST pin supported
Low/medium/high speed oscillator (external crystal or resonator)
7.16.1 Port configurations
All but three I/O port pins on the P89LPC970/971/972 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. 1. P1.5/RST can only be an input and cannot be configured. 2. P1.2/SCL/T0 and P1.3/INT0/SDA/T4 may only be configured to be either input-only or open-drain. 7.16.1.1 Quasi-bidirectional output configuration Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression circuit. 7.16.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open-drain port pin has a Schmitt trigger input that also has a glitch suppression circuit.
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7.16.1.3
Input-only configuration The input-only port configuration has no output drivers. It is a Schmitt trigger input that also has a glitch suppression circuit.
7.16.1.4
Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit. The P89LPC970/971/972 device has high current source on eight pins in push-pull mode. See Table 10 "Limiting values".
7.16.2 Port 0 analog functions
The P89LPC970/971/972 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the input-only (high-impedance) mode. Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
7.16.3 Additional port features
After power-up, all pins are in input-only mode. Please note that this is different from the LPC76x series of devices.
* After power-up, all I/O pins except P1.5, may be configured by software. * Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or
open-drain. Every output on the P89LPC970/971/972 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 11 "Static characteristics" for detailed specifications. All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
7.16.4 Pin remap
This feature allows the functions of UART/I2C/SPI to be remapped to other pins. Configuration register controls the multiplexers to allow connection between the pins and the on chip peripherals. See Table 8 "SPI/I2C/UART pin remap". UART/I2C/SPI, each has two options of pin configuration: primary pin map and alternative pin map. After reset, UART/I2C/SPI chooses the primary pin map as default. User can adjust to the alternative pin map through configuring PINCON register according to the application. Please refer to P89LPC970/971/972 User manual for detail configurations.
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SPI/I2C/UART pin remap Function SPICLK MOSI MISO SS Primary pin out P1.3 P1.2 P1.0 P1.1 Alternative pin out P0.0 P1.7 P1.6 P1.4 -
Table 8. SPI
Peripherals
I2C UART
SDA SCL TXD RXD
7.17 Power management
The P89LPC970/971/972 support a variety of power management features. Power-on detect and brownout detect are designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. The P89LPC970/971/972 support three different power reduction modes: Idle mode, Power-down mode, and total Power-down mode. In addition, individual on-chip peripherals can be disabled to eliminate unnecessary dynamic power use in any peripherals that are not required for the application. Integrated PMU automatically adjusts internal regulators to minimize power consumption during Idle mode, Power-down mode and total Power-down mode. In addition, the power consumption can be further reduced in Normal or Idle mode through configuring regulators mode according to the applications.
7.17.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced brownout detection has 3 independent functions: BOD reset, BOD interrupt and BOD flash. These three functions are disabled in Power-down mode and Total Power-down mode. In Normal or Idle mode, BOD reset and BOD flash are always on and can not be disabled in software. BOD interrupt may be enabled or disabled in software. BOD reset and BOD interrupt, each has 6 levels. BOE0 to BOE2 (UCFG1[3:5]) are used as trip point configuration bits of BOD reset. BOICFG0 to BOICFG2 in register BODCFG are used as trip point configuration bits of BOD interrupt. BOD reset voltage should be lower than BOD interrupt trip point. BOD flash is used for flash programming/erase protection and has only 1 trip point at 2.4 V. Please refer to P89LPC970/971/972 User manual for detail configurations. If brownout detection works, the brownout condition occurs when VDD falls below the brownout falling trip voltage and is negated when VDD rises above the brownout rising trip voltage. For correct activation of brownout detect, the VDD rise and fall times must be observed. Please see Table 11 "Static characteristics" for specifications.
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8-bit microcontroller with accelerated two-clock 80C51 core
7.17.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially to ensure that the device is reset from Power-on. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
7.17.3 Power reduction modes
The P89LPC970/971/972 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode. 7.17.3.1 Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode. 7.17.3.2 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. Brownout detection circuitry is disabled. The P89LPC970/971/972 exits Power-down mode via any reset, or certain interrupts. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators and RTC/system timer (note that watchdog timer, comparators and RTC/system timer can be powered down separately). The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. 7.17.3.3 Total Power-down mode The total Power-down mode is a deeper power reduction mode. Brownout detection circuitry and analog comparators are disabled, as well as the internal RC oscillator. Please use an external low frequency clock or 25 kHz watchdog oscillator to achieve low power with the RTC running during power-down.
7.17.4 Regulators
Internal regulators can be adjusted automatically to minimize power consumption during different power reduction modes. In Normal or Idle modes, power consumption can be further reduced by configuring PMUCON register. In Normal or Idle mode, regulators have two operation modes: High-speed mode and Low current mode. The regulators can be configured to Low current mode to reduce the power consumption. After power-on-reset, internal regulators enter into High-speed mode as default. PMUCON register is used to configure the regulators operation modes. LPMOD bit is used to select the regulator's mode and HCOK bit indicates whether the switch completed or not. When switching back to high speed mode, first clear LPMOD bit to select high speed mode, then check HCOK bit. If HCOK bit turns to `1', it means the switch was completed.
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7.18 Reset
The P1.5/RST pin can function as either a LOW-active reset input or as a digital input, P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin always functions as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this pin will function as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Reset can be triggered from the following sources:
* * * * * *
External reset pin (during power-up or if user configured via UCFG1) Power-on detect Brownout detect Watchdog timer Software reset UART break character detect reset
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
* During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
* A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the
other flag bits are cleared.
* For any other reset, previously set flag bits that have not been cleared will remain set.
7.18.1 Reset vector
Following reset, the P89LPC970/971/972 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see P89LPC970/971/972 User manual). Otherwise, instructions will be fetched from address 0000H.
7.19 Timers/counters 0 and 1
The P89LPC970/971/972 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters. An option to automatically toggle the T0 or T1 pins upon timer overflow has been added. In the `Timer' function, the register is incremented every machine cycle.
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In the `Counter' function, the register is incremented in response to a 1-to-0 transition at its corresponding count input pin, T0 or T1. In this function, the count input is sampled once during every machine cycle. Timer 0 and Timer 1 have five operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.
7.19.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
7.19.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.19.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1. 7.19.3.1 Mode 3 When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator. 7.19.3.2 Mode 6 In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
7.19.4 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
7.20 Timers/counters 2, 3 and 4
The P89LPC970/971/972 has three external 16-bit timer/counters. All can be configured to operate either as timers or event counters. An option to automatically toggle pin Tx (x = 2, 3 or 4) upon timer overflow has been added. In the `Timer' function, the register is incremented every PCLK. In the `Counter' function, the register is incremented in response to a 1-to-0 transition at its corresponding count input pin (T2/T3 /T4). In this function, the count input is sampled once during every machine cycle. Only external Timer 2/3/4 has the external input pin TxEX (x = 2, 3 or 4). A 1-to-0 transition on this pin can trigger a reload or capture event. Timer 2, Timer 3 and Timer 4 have three operating modes (Modes 0, 1 and 2).
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7.20.1 Mode 0: 16-bit timer/counter with auto-reload
Mode 0 configures the timer register as an 16-bit Timer/counter with automatic reload. An overflow upon the timer or a 1-to-0 transition at TxEX pin can cause the reload event.
7.20.2 Mode 1: 16-bit timer/counter with input capture
Mode 1 configures the timer register as an 16-bit Timer/counter with input capture. A 1-to-0 transition at TxEX pin can cause the capture event.
7.20.3 Mode 2: 16-bit PWM mode
In this mode, the corresponding timer can be changed to a 16-bit PWM generator with adjustable duty cycle. In this mode, the corresponding timer can be changed to a 16-bit PWM generator with adjustable duty cycle and adjustable full period (from 0, theoretically, to 131072).
7.20.4 Timer overflow toggle output
Timers 2, 3 and 4 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T2, T3 and T4 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
7.21 RTC/system timer
The P89LPC970/971/972 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog reset will reset the RTC and its associated SFRs to the default state. The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and RTCDATH registers.
7.22 UART
The P89LPC970/971/972 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC970/971/972 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent baud rate generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.22.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency.
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7.22.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in special function register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.22.5 "Baud rate generator and selection").
7.22.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.
7.22.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the baud rate generator (described in Section 7.22.5 "Baud rate generator and selection").
7.22.5 Baud rate generator and selection
The P89LPC970/971/972 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 7). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent baud rate generators use OSCCLK.
timer 1 overflow (PCLK-based) /2
SMOD1 = 1
SBRGS = 0 baud rate modes 1 and 3
SMOD1 = 0 baud rate generator (CCLK-based)
SBRGS = 1
002aaa897
Fig 7.
Baud rate sources for UART (Modes 1, 3)
7.22.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0.
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7.22.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.
7.22.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).
7.22.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated when the double buffer is ready to receive new data.
7.22.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TI interrupt. If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.
7.23 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:
* Bidirectional data transfer between masters and slaves * Multi master bus (no central master) * Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
* Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
* Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
* The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 8. The P89LPC970/971/972 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
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8-bit microcontroller with accelerated two-clock 80C51 core
RP
RP
SDA I2C-bus SCL P1.3/SDA P1.2/SCL
P89LPC970/971/972
OTHER DEVICE WITH I2C-BUS INTERFACE
OTHER DEVICE WITH I2C-BUS INTERFACE
002aaf092
Fig 8.
I2C-bus configuration
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8
ADDRESS REGISTER P1.3
I2ADR
COMPARATOR INPUT FILTER P1.3/SDA OUTPUT STAGE SHIFT REGISTER ACK I2DAT 8
CCLK TIMING AND CONTROL LOGIC interrupt
INPUT FILTER P1.2/SCL OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL
SERIAL CLOCK GENERATOR
CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS 8
status bus
STATUS DECODER
I2STAT
STATUS REGISTER
8
002aaa899
Fig 9.
I2C-bus serial interface block diagram
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INTERNAL BUS
BIT COUNTER / ARBITRATION AND SYNC LOGIC
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
7.24 SPI (Pin remap)
The P89LPC970/971/972 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.
S M CPU clock 8-BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER M S PIN CONTROL LOGIC
MISO P1.6 MOSI P1.7 SPICLK P0.0 SS P1.4 SPEN
002aaf091
(c) NXP B.V. 2010. All rights reserved.
SPI clock (master) SELECT SPR1 SPR0
clock CLOCK LOGIC S M MSTR DORD MSTR CPHA SPEN CPOL SPR1 SPI CONTROL REGISTER internal data bus
SPI CONTROL WCOL SPIF
MSTR SPEN SPR0 SSIG SPI interrupt request
SPI STATUS REGISTER
Fig 10. SPI block diagram
The SPI interface has four pins: SPICLK, MOSI, MISO and SS:
* SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e., SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
* SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 11 through Figure 13.
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7.24.1 Typical SPI configurations
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR PORT
SPICLK SS
002aaa901
Fig 11. SPI single master single slave configuration
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR SS
SPICLK SS SPI CLOCK GENERATOR
002aaa902
Fig 12. SPI dual device configuration, where either can be a master or a slave
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master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR port
SPICLK SS
slave MISO MOSI 8-BIT SHIFT REGISTER
SPICLK port SS
002aaa903
Fig 13. SPI single master multiple slaves configuration
7.25 Analog comparators
Two analog comparators are provided on the P89LPC970/971/972. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. The overall connections to both comparators are shown in Figure 14. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 s. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. When a comparator is disabled the comparator's output, COn, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFn, after disabling the comparator.
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CP1 (P0.4) CIN1A (P0.3) CIN1B (P0.5) CMPREF Vref(cmp)(1) CN1 change detect CMF1 comparator 1 CO1 OE1
CMP1 (P0.6)
interrupt change detect CP2 CMF2 (P0.2) CIN2A (P0.1) CIN2B CMP2 (P0.0) CO2 OE2 CN2
002aac346
EC
comparator 2
(1) See Section 7.25.1 for more details.
Fig 14. Comparator input and output connections
7.25.1 Selectable internal reference voltage
An internal reference voltage generator may be used to supply a default reference when a single comparator input pin is used. The user may program one of eight different values for the internal reference voltage using the Comparator Reference register (CMPREF). Each of the two comparators may use a different reference voltage.
7.25.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt.
7.25.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.
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7.26 KBI
The Keypad Interrupt function (KBI) is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The port can be configured via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison. In order to use the Keypad Interrupt as an original KBI function like in P87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs.
7.27 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler can be the PCLK, the nominal 400 kHz/25 kHz watchdog oscillator or crystal oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 15 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC970/971/972 User manual for more details.
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WDL (C1H)
MOV WFEED1, #0A5H MOV WFEED2, #05AH 400 kHz oscillator 25 kHz oscillator
PCLK 0 1 watchdog oscillator
0 0 1 crystal oscillator 1 /32 PRESCALER 8-BIT DOWN COUNTER reset(1)
XTALWD (CLKCON.4) WDMOD (CLKCON.5)
SHADOW REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aae542
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.
Fig 15. Watchdog timer in Watchdog mode (WDTE = 1)
7.28 Additional features
7.28.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.
7.28.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
7.29 Flash program memory
7.29.1 General description
The P89LPC970/971/972 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte-erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC970/971/972 flash reliably stores memory contents even after 100000 erase and program cycles. The cell is designed to
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
optimize the erase and programming mechanisms. The P89LPC970/971/972 uses VDD as the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD flash is tripped and flash erase/program is blocked.
7.29.2 Features
* * * * *
Programming and erase over the full operating voltage range. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ISP/IAP/ICP. Internal fixed boot ROM, containing low-level IAP routines available to user code. Default loader providing ISP via the serial port, located in upper end of user program memory. memory space, providing flexibility to the user.
* Boot vector allows user-provided flash loader code to reside anywhere in the flash * * * * *
Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. 100000 typical erase/program cycles for each byte. 10 year minimum data retention.
7.29.3 Flash organization
The program memory consists of two/four/eight 1 kB sectors on the P89LPC970/971/972 device. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time.
7.29.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.
7.29.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP) under control of the application's firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock/serial data interface. As shipped from the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for the device to be programmed in circuit through the serial port. The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire user code space. Remark: When voltage supply is lower than 2.4 V, the BOD flash is tripped and flash erase/program is blocked.
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8-bit microcontroller with accelerated two-clock 80C51 core
7.29.6 ICP
ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC970/971/972 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC970/971/972 User manual.
7.29.7 IAP
IAP is performed in the application under the control of the microcontroller's firmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The NXP IAP has made in-application programming in an embedded application possible without additional components. Two methods are available to accomplish IAP. A set of predefined IAP functions are provided in a Boot ROM and can be called through a common interface, PGM_MTP. Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, configuration bytes, and device ID. These functions are selected by setting up the microcontroller's registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the program memory space at the top of the address space from FF00H to FEFFH, thereby not conflicting with the user program memory space. In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC970/971/972 User manual.
7.29.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC970/971/972 through the serial port. This firmware is provided by NXP and embedded within each P89LPC970/971/972 device. The NXP ISP facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TXD, RXD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.
7.29.9 Power-on reset code execution
The P89LPC970/971/972 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC970/971/972 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user's application code. When the Boot Status bit is set to a value other than zero, the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to 00H. Table 9 shows the factory default Boot Vector setting for these devices. A factory-provided bootloader is pre-programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions. This code can be erased by the user.
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
Remark: Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader. Instead, the page erase function can be used to erase the first eight 64-byte pages located in this sector. A custom bootloader can be written with the Boot Vector set to the custom bootloader, if desired.
Table 9. Device Default boot vector values and ISP entry points Default boot vector 07H 0FH 1FH Default bootloader entry point 0700H 0F00H 1F00H Default bootloader code range 0600H to 07FFH 0E00H to 1FFFH 1E00H to 1FFFH 1 kB sector range 0400H to 07FFH 0C00H to 0FFFH 1C00H to 1FFFH
P89LPC970 P89LPC971 P89LPC972
7.29.10 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a power-on sequence (see the P89LPC970/971/972 User manual for specific information). This has the same effect as having a non-zero status byte. This allows an application to be built that will normally execute user code but can be manually forced into ISP operation. If the factory default setting for the boot is changed, it will no longer point to the factory pre-programmed ISP bootloader code. After programming the flash, the status byte should be programmed to zero in order to allow execution of the user's application code beginning at address 0000H.
7.30 User configuration bytes
Some user-configurable features of the P89LPC970/971/972 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1 and UCFG2. Please see the P89LPC970/971/972 User Manual for additional details.
7.31 User sector security bytes
There are four/eight User Sector Security Bytes on the P89LPC970/971/972. Each byte corresponds to one sector. Please see the P89LPC970/971/972 User manual for additional details.
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
8. Limiting values
Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg IOH(I/O) IOL(I/O) II/Otot(max) Vxtal Parameter bias ambient temperature storage temperature HIGH-level output current per input/output pin LOW-level output current per input/output pin maximum total input/output current crystal voltage on XTAL1, XTAL2 pins when XTAL1/XTAL2 is used as crystal input/output; with respect to VSS on XTAL1, XTAL2 pins when XTAL1/XTAL2 is used as GPIO; with respect to VSS Vn Ptot(pack) voltage on any other pin total power dissipation (per package) with respect to VSS based on package heat transfer, not device power consumption human body model; all pins charged device model; all pins
[1] The following applies to Table 10: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[2]
Conditions
Min -55 -65 -0.5
Max +125 +150 20 20 100 +4.0
Unit C C mA mA mA V
-0.5
+5.5
V
-
5.5 1.5
V W
VESD
electrostatic discharge voltage
-3000 -700
+3000 +700
V V
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
system frequency (MHz) 18
12
2.4
2.7
3.0
3.3
3.6 VDD (V)
5.5
002aaf005
Fig 16. Frequency vs. supply voltage
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
9. Static characteristics
Table 11. Static characteristics VDD = 2.4 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol IDD(oper) Parameter operating supply current Conditions VDD = 2.4 V fosc = 12 MHz, High-speed mode of regulators fosc = 12 MHz, Low current mode of regulators VDD = 3.3 V fosc = 12 MHz, High-speed mode of regulators fosc = 12 MHz, Low current mode of regulators VDD = 5.5 V fosc = 12 MHz, High-speed mode of regulators fosc = 12 MHz, Low current mode of regulators fosc = 18 MHz, High-speed mode of regulators IDD(idle) Idle mode supply current VDD = 2.4 V fosc = 12 MHz, High-speed mode of regulators fosc = 12 MHz, Low current mode of regulators VDD = 3.3 V fosc = 12 MHz, High-speed mode of regulators fosc = 12 MHz, Low current mode of regulators VDD = 5.5 V fosc = 12 MHz, High-speed mode of regulators fosc = 12 MHz, Low current mode of regulators fosc = 18 MHz, High-speed mode of regulators IDD(pd) Power-down mode VDD = 2.4 V; voltage comparators supply current powered down VDD = 3.3 V; voltage comparators powered down VDD = 5.5 V; voltage comparators powered down
[2] [2] [2] [2] [2] [2]
Min -
Typ[1] 6 5
Max 7 6
Unit mA mA
[2]
-
9 7
10 8
mA mA
[2]
-
10 8 11
11 9 12
mA mA mA
[2]
[2]
-
3.5 3
4.5 4
mA mA
[2]
-
5 4
6 5
mA mA
[2]
-
6 4 6.5 28 32 38
7 5 7.5 35 40 45
mA mA mA A A A
[2]
[2]
[3]
[3]
[3]
P89LPC97X_2
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
Table 11. Static characteristics ...continued VDD = 2.4 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol IDD(tpd) Parameter total Power-down mode supply current rise rate fall rate power-on reset voltage data retention supply voltage HIGH-LOW threshold voltage LOW-level input voltage LOW-HIGH threshold voltage HIGH-level input voltage hysteresis voltage LOW-level output voltage except SCL, SDA SCL, SDA only except SCL, SDA SCL, SDA only port 1 IOL = 20 mA; VDD = 2.4 V to 5.5 V all ports, all modes except high-Z IOL = 3.2 mA; VDD = 2.4 V to 5.5 V all ports, all modes except high-Z VOH HIGH-level output voltage IOH = -20 A; VDD = 2.4 V to 5.5 V; all ports, quasi-bidirectional mode IOH = -3.2 mA; VDD = 2.4 V to 5.5 V; all ports, push-pull mode IOH = -10 mA; VDD = 2.4 V to 5.5 V; all ports, push-pull mode Vxtal crystal voltage on XTAL1, XTAL2 pins when XTAL1/XTAL2 is used as crystal input/output; with respect to VSS on XTAL1, XTAL2 pins when XTAL1/XTAL2 is used as GPIO; with respect to VSS Vn Ciss IIL ILI ITHL voltage on any other pin input capacitance LOW-level input current input leakage current HIGH-LOW transition current VI = 0.4 V VI = VIL, VIH, or Vth(HL) all ports; VI = 1.5 V at VDD = 5.5 V with respect to VSS
[5] [4]
Conditions VDD = 2.4 V VDD = 3.3 V VDD = 5.5 V of VDD; to ensure power-on reset signal of VDD
[3] [3] [3]
Min 5 1.5 0.22VDD -0.5 0.55VDD VDD - 0.3 VDD - 0.7 -0.5
Typ[1] 1 1 1 0.4VDD 0.6VDD 0.2VDD 0.6 0.2 VDD - 0.2 VDD - 0.4 VDD - 0.5 -
Max 5 5 5 5000 50 0.5 0.4VDD 0.7VDD 5.5 1.0 0.3 +4.0
Unit A A A V/S mV/s V V V V V V V V V V V V V
(dV/dt)r (dV/dt)f VPOR VDDR Vth(HL) VIL Vth(LH) VIH Vhys VOL
[4]
-0.5
-
+5.5
V
-0.5 -30
-
+5.5 15 -80 1 -450
V pF A A A
[6] [7]
[8]
[9]
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8-bit microcontroller with accelerated two-clock 80C51 core
Table 11. Static characteristics ...continued VDD = 2.4 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol Parameter Conditions pin RST Min 30 Typ[1] Max 120 Unit k RRST_N(int) internal pull-up resistance on pin RST BOD interrupt Vtrip trip voltage falling stage BOICFG2, BOICFG1, BOICFG0 = 010 BOICFG2, BOICFG1, BOICFG0 = 011 BOICFG2, BOICFG1, BOICFG0 = 100 BOICFG2, BOICFG1, BOICFG0 = 101 BOICFG2, BOICFG1, BOICFG0 = 110 BOICFG2, BOICFG1, BOICFG0 = 111 rising stage BOICFG2, BOICFG1, BOICFG0 = 010 BOICFG2, BOICFG1, BOICFG0 = 011 BOICFG2, BOICFG1, BOICFG0 = 100 BOICFG2, BOICFG1, BOICFG0 = 101 BOICFG2, BOICFG1, BOICFG0 = 110 BOICFG2, BOICFG1, BOICFG0 = 111 2.60 2.90 3.05 3.50 4.15 4.35 2.80 3.10 3.25 3.70 4.35 4.55 V V V V V V 2.45 2.75 2.90 3.35 4.10 4.25 2.65 2.95 3.10 3.55 4.30 4.45 V V V V V V
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
Table 11. Static characteristics ...continued VDD = 2.4 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol BOD reset Vtrip trip voltage falling stage BOE2, BOE1, BOE0 = 010 BOE2, BOE1, BOE0 = 011 BOE2, BOE1, BOE0 = 100 BOE2, BOE1, BOE0 = 101 BOE2, BOE1, BOE0 = 110 BOE2, BOE1, BOE0 = 111 rising stage BOE2, BOE1, BOE0 = 010 BOE2, BOE1, BOE0 = 011 BOE2, BOE1, BOE0 = 100 BOE2, BOE1, BOE0 = 101 BOE2, BOE1, BOE0 = 110 BOE2, BOE1, BOE0 = 111 BOD flash Vtrip Vref(bg) TCbg trip voltage band gap reference voltage band gap temperature coefficient falling stage rising stage 2.30 2.40 1.19 1.23 10 2.55 2.65 1.27 20 V V V ppm/ C 2.30 2.60 2.90 3.20 3.85 4.05 2.50 2.80 3.10 3.40 4.05 4.25 V V V V V V 2.15 2.45 2.75 3.05 3.75 3.95 2.35 2.65 2.95 3.25 3.95 4.15 V V V V V V Parameter Conditions Min Typ[1] Max Unit
[1] [2] [3] [4] [5]
Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. The IDD(oper) and IDD(idle) specifications are measured using an external clock with the following functions disabled: comparators, real-time clock, and watchdog timer. The IDD(pd) and IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock, brownout detect, and watchdog timer. See Section 8 "Limiting values" for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition, VOL/VOH may exceed the related specification. This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with respect to VSS. Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode. Measured with port in high-impedance mode. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V.
[6] [7] [8] [9]
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10. Dynamic characteristics
Table 12. Dynamic characteristics (12 MHz) VDD = 2.4 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON, VDD = 2.7 V to 5.5 V fosc(WD) fosc Tcy(clk) fCLKLP Glitch filter tgr tsa glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI operating frequency slave master 0 CCLK CCLK 6 4
Variable clock Min 7.189 Max 7.557
fosc = 12 MHz Min 7.189 Max
Unit
7.557 MHz
14.378
15.114
14.378 15.114 MHz
internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency see Figure 17
360 0 83 0
440 12 8
360 -
440 -
kHz MHz ns MHz
125 50 33 33 16Tcy(clk) 13Tcy(clk) 150
50 15 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 8 8 Tcy(clk) + 20 0 -
125 50 33 33 1333 1083 150
50 15 8 8 103 0 -
ns ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 17 see Figure 17 see Figure 17 see Figure 17 see Figure 18 see Figure 18 see Figure 18 see Figure 18 see Figure 18
Shift register (UART mode 0)
SPI interface fSPI 0 2.0 3.0 MHz MHz
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8-bit microcontroller with accelerated two-clock 80C51 core
Table 12. Dynamic characteristics (12 MHz) ...continued VDD = 2.4 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol TSPICYC Parameter SPI cycle time slave master tSPILEAD tSPILAG tSPICLKH SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time master slave tSPICLKL SPICLK LOW time master slave tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 19, 20, 21, 22
6 4
Variable clock Min Max 120 240
fosc = 12 MHz Min 500 333 250 250 165 250 165 250 100 100 0 Max 120 240
Unit
CCLK CCLK
ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 21, 22 250 see Figure 21, 22 250 see Figure 19, 20, 21, 22
2 3 CCLK CCLK
see Figure 19, 20, 21, 22
2 3 CCLK CCLK
see Figure 19, 20, 21, 22 100 see Figure 19, 20, 21, 22 100 see Figure 21, 22 0 see Figure 21, 22 0 see Figure 19, 20, 21, 22 see Figure 19, 20, 21, 22 see Figure 19, 20, 21, 22 see Figure 19, 20, 21, 22 100 2000 100 2000 ns ns 100 2000 100 2000 ns ns 0 240 167 0 240 167 ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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8-bit microcontroller with accelerated two-clock 80C51 core
Table 13. Dynamic characteristics (18 MHz) VDD = 3.6 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol Parameter fosc(RC) internal RC oscillator frequency Conditions nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C; clock doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = ON fosc(WD) fosc Tcy(clk) fCLKLP internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency glitch rejection time signal acceptance time P1.5/RST pin any pin except P1.5/RST tsa P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time output data set-up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI operating frequency slave master TSPICYC SPI cycle time slave master see Figure 19, 20, 21, 22
6 4 CCLK CCLK
Variable clock Min 7.189 Max 7.557
fosc = 18 MHz Min 7.189 Max
Unit
7.557 MHz
14.378 360 0
15.114 440 18 8
14.378 15.114 MHz 360 440 kHz MHz ns MHz
see Figure 17
55 0
Glitch filter tgr 125 50 22 22 16Tcy(clk) 13Tcy(clk) 150 50 15 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 5 5 Tcy(clk) + 20 0 125 50 22 22 888 722 150 50 15 5 5 75 0 ns ns ns ns ns ns ns ns ns ns ns ns ns
see Figure 17 see Figure 17 see Figure 17 see Figure 17 see Figure 18 see Figure 18 see Figure 18 see Figure 18 see Figure 18
Shift register (UART mode 0)
SPI interface fSPI 0 CCLK CCLK
6 4
0 333 222
3.0 4.5 -
MHz MHz ns ns
-
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8-bit microcontroller with accelerated two-clock 80C51 core
Table 13. Dynamic characteristics (18 MHz) ...continued VDD = 3.6 V to 5.5 V unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified.[1][2] Symbol Parameter tSPILEAD tSPILAG tSPICLKH SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time slave master tSPICLKL SPICLK LOW time slave master tSPIDSU tSPIDH tSPIA tSPIDIS tSPIDV SPI data set-up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 21, 22
Variable clock Min 250 Max 80 160
fosc = 18 MHz Min 250 250 167 111 167 111 100 100 0 Max 80 160
Unit
ns ns ns ns ns ns ns ns ns ns
see Figure 21, 22 250 see Figure 19, 20, 21, 22
3 2 CCLK CCLK
see Figure 19, 20, 21, 22
3 2 CCLK CCLK
see Figure 19, 20, 21, 22 100 see Figure 19, 20, 21, 22 100 see Figure 21, 22 0 see Figure 21, 22 0 see Figure 19, 20, 21, 22 see Figure 19, 20, 21, 22 see Figure 19, 20, 21, 22 see Figure 19, 20, 21, 22 100 2000 100 2000 ns ns 100 2000 100 2000 ns ns 0 160 111 0 160 111 ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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8-bit microcontroller with accelerated two-clock 80C51 core
10.1 Waveforms
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
TXLXL clock tQVXH output data 0 write to SBUF input data clear RI set RI
002aaa906
tXHQX 1 tXHDX 2 3 4 5 6 7
tXHDV
valid valid valid valid valid valid valid
set TI
valid
Fig 18. Shift register mode timing
SS TSPICYC tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR master MSB/LSB out master LSB/MSB out
002aaa908
tSPICLKL
tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF
Fig 19. SPI master timing (CPHA = 0)
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8-bit microcontroller with accelerated two-clock 80C51 core
SS TSPICYC tSPIF tSPICLKL tSPIR tSPICLKH
SPICLK (CPOL = 0) (output) tSPIF SPICLK (CPOL = 1) (output) tSPICLKH tSPICLKL tSPIR
tSPIDSU MISO (input)
tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF master MSB/LSB out master LSB/MSB out
002aaa909
Fig 20. SPI master timing (CPHA = 1)
SS
tSPIF tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIA tSPIOH tSPIDV MISO (output) tSPIF
TSPICYC tSPICLKH tSPICLKL tSPIR tSPILAG
tSPIR
tSPICLKL
tSPIR tSPICLKH
tSPIOH tSPIDV
tSPIOH
tSPIDIS
slave MSB/LSB out
slave LSB/MSB out
not defined
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa910
Fig 21. SPI slave timing (CPHA = 0)
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
SS tSPIF tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIOH tSPIDV tSPIA MISO (output) not defined slave MSB/LSB out slave LSB/MSB out tSPICLKL tSPIR tSPICLKH tSPIF tSPICLKH tSPIR tSPIR tSPILAG
TSPICYC tSPICLKL
tSPIOH tSPIDV
tSPIOH tSPIDV tSPIDIS
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa911
Fig 22. SPI slave timing (CPHA = 1)
10.2 ISP entry mode
Table 14. Dynamic characteristics, ISP entry mode VDD = 2.4 V to 5.5 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol tVR tRH tRL Parameter VDD active to RST active delay time RST HIGH time RST LOW time Conditions pin P1.5/RST pin P1.5/RST pin P1.5/RST Min 50 1 1 Typ Max 32 Unit s s s
VDD tVR RST tRL
002aaa912
tRH
Fig 23. ISP entry waveform
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8-bit microcontroller with accelerated two-clock 80C51 core
11. Other characteristics
11.1 Comparator electrical characteristics
Table 15. Comparator electrical characteristics VDD = 2.4 V to 5.5 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol VIO VIC CMRR tres(tot) t(CE-OV) ILI
[1]
Parameter input offset voltage common-mode input voltage common-mode rejection ratio total response time chip enable to output valid time input leakage current
Conditions
Min 0
[1]
Typ 250 -
Max 10 VDD - 0.3 -50 500 10 1
Unit mV V dB ns s A
-
0 V < VI < VDD
-
This parameter is characterized, but not tested in production.
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8-bit microcontroller with accelerated two-clock 80C51 core
12. Package outline
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 24. TSSOP20 package outline (SOT360-1)
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.1
e1 7.62 0.3
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC MS-001 JEITA SC-603 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 25. DIP20 package outline (SOT146-1)
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8-bit microcontroller with accelerated two-clock 80C51 core
13. Abbreviations
Table 16. Acronym CCU CPU CRC DAC EEPROM EMI EPROM GPIO IRC LSB MSB PGA PLL PWM RAM RC RTC SAR SFR SPI UART WDT Abbreviations Description Capture/Compare Unit Central Processing Unit Cyclic Redundancy Check Digital to Analog Converter Electrically Erasable Programmable Read-Only Memory Electro-Magnetic Interference Erasable Programmable Read-Only Memory General Purpose Input/Output Internal RC Least Significant Bit Most Significant Bit Programmable Gain Amplifier Phase-Locked Loop Pulse Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Successive Approximation Register Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter Watchdog Timer
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14. Revision history
Table 17. Revision history Release date 20100427 Data sheet status Product data sheet Change notice Supersedes P89LPC97X_1 Document ID P89LPC97X_2 Modifications:
* * *
Changed data sheet status to `Product data sheet'. Table 11 "Static characteristics": Updated Min/Typ/Max values for BOD interrupt and BOD reset. Table 11 "Static characteristics": Updated conditions and Min/Max/Unit values for (dV/dt)r. Preliminary data sheet -
P89LPC97X_1
20091217
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8-bit microcontroller with accelerated two-clock 80C51 core
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the
(c) NXP B.V. 2010. All rights reserved.
15.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
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8-bit microcontroller with accelerated two-clock 80C51 core
product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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8-bit microcontroller with accelerated two-clock 80C51 core
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 10 7.1 Special function registers . . . . . . . . . . . . . . . . 10 7.2 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.1 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 19 7.3.2 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 19 7.4 Crystal oscillator option. . . . . . . . . . . . . . . . . . 19 7.4.1 Low speed oscillator option . . . . . . . . . . . . . . 19 7.4.2 Medium speed oscillator option . . . . . . . . . . . 19 7.4.3 High speed oscillator option . . . . . . . . . . . . . . 19 7.5 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 On-chip RC oscillator option . . . . . . . . . . . . . . 20 7.7 Watchdog oscillator option . . . . . . . . . . . . . . . 20 7.8 External clock input option . . . . . . . . . . . . . . . 20 7.9 Clock source switching on the fly . . . . . . . . . . 20 7.10 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 21 7.11 CCLK modification: DIVM register . . . . . . . . . 21 7.12 Low power select . . . . . . . . . . . . . . . . . . . . . . 21 7.13 Memory organization . . . . . . . . . . . . . . . . . . . 22 7.14 Data RAM arrangement . . . . . . . . . . . . . . . . . 22 7.15 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15.1 External interrupt inputs . . . . . . . . . . . . . . . . . 23 7.16 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.16.1 Port configurations . . . . . . . . . . . . . . . . . . . . . 25 7.16.1.1 Quasi-bidirectional output configuration . . . . . 25 7.16.1.2 Open-drain output configuration . . . . . . . . . . . 25 7.16.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 26 7.16.1.4 Push-pull output configuration . . . . . . . . . . . . 26 7.16.2 Port 0 analog functions . . . . . . . . . . . . . . . . . . 26 7.16.3 Additional port features. . . . . . . . . . . . . . . . . . 26 7.16.4 Pin remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.17 Power management . . . . . . . . . . . . . . . . . . . . 27 7.17.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 27 7.17.2 Power-on detection. . . . . . . . . . . . . . . . . . . . . 28 7.17.3 Power reduction modes . . . . . . . . . . . . . . . . . 28 7.17.3.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.17.3.2 7.17.3.3 7.17.4 7.18 7.18.1 7.19 7.19.1 7.19.2 7.19.3 7.19.3.1 7.19.3.2 7.19.4 7.20 7.20.1 7.20.2 7.20.3 7.20.4 7.21 7.22 7.22.1 7.22.2 7.22.3 7.22.4 7.22.5 7.22.6 7.22.7 7.22.8 7.22.9 7.22.10 7.23 7.24 7.24.1 7.25 7.25.1 7.25.2 7.25.3 7.26 7.27 7.28 7.28.1 7.28.2 7.29 7.29.1 7.29.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . Total Power-down mode . . . . . . . . . . . . . . . . Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . Timers/counters 0 and 1 . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer overflow toggle output . . . . . . . . . . . . . Timers/counters 2, 3 and 4 . . . . . . . . . . . . . . Mode 0: 16-bit timer/counter with auto-reload. . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1: 16-bit timer/counter with input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2: 16-bit PWM mode . . . . . . . . . . . . . . Timer overflow toggle output . . . . . . . . . . . . . RTC/system timer . . . . . . . . . . . . . . . . . . . . . UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection. . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering. . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . The 9th bit (bit 8) in double buffering (modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . I2C-bus serial interface. . . . . . . . . . . . . . . . . . SPI (Pin remap) . . . . . . . . . . . . . . . . . . . . . . . Typical SPI configurations . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Selectable internal reference voltage. . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparators and power reduction modes . . . KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 28 28 29 29 29 30 30 30 30 30 30 30 31 31 31 31 31 31 31 32 32 32 32 32 33 33 33 33 33 36 37 38 39 39 39 40 40 41 41 41 41 41 42
continued >>
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8-bit microcontroller with accelerated two-clock 80C51 core
42 42 42 43 43 43 43 44 44 44 45 47 51 55 57 58 58 59 61 62 63 63 63 63 64 64 65
7.29.3 7.29.4 7.29.5 7.29.6 7.29.7 7.29.8 7.29.9 7.29.10 7.30 7.31 8 9 10 10.1 10.2 11 11.1 12 13 14 15 15.1 15.2 15.3 15.4 16 17
Flash organization . . . . . . . . . . . . . . . . . . . . . Using flash as data storage . . . . . . . . . . . . . . Flash programming and erasing . . . . . . . . . . . ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on reset code execution . . . . . . . . . . . Hardware activation of the bootloader . . . . . . User configuration bytes . . . . . . . . . . . . . . . . . User sector security bytes . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . ISP entry mode . . . . . . . . . . . . . . . . . . . . . . . . Other characteristics . . . . . . . . . . . . . . . . . . . . Comparator electrical characteristics . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 April 2010 Document identifier: P89LPC97X_2

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